The present invention relates to a semiconductor integrated circuit device and, more particularly, to a testing circuit for a semiconductor integrated circuit device employing a scan pass.
The integration of a semiconductor integrated circuit device has been remarkably improved by microminiaturization and is expected to be further enhanced in future. A difficulty of testing the semiconductor integrated circuit device has been exponentially increased as this level of integration (number of gates) has been increased. The degree of the ease of testing the semiconductor integrated circuit is determined by two points of the difficulty (observance) of observing the defect of each terminal and the difficulty (controllability) of setting each terminal to a desired logic value-and the deep internal terminal of a large-scale logic circuit network has associated problems in both observance and controllability.
The scan testing system for a semiconductor integrated circuit device is known. The scan testing system improves the observance and the controllability of the deep terminal of the large-scale logic circuit network by observing the large-scale logic circuit network through inserting register circuits each including a shift register function into proper positions of the logic circuit network, connecting the register circuits in series, serially inputting a test pattern from the exterior of a chip at testing time to load predetermined data into the registers, applying a desired logic signal to the logic circuit connected to the data output terminals of the registers to operate the logic circuit, inputting the result from the parallel input terminals of the registers in parallel in the registers, and then serially outputting them out of the chip to observe them.
A fundamental idea of a scan testing system regarding a level sensitive synchronizer circuit is disclosed in Japanese Patent Laid-open No. 28614/1977.
Since the circuit to be observed includes asynchronous sequential circuit here, the scan testing system will be described with reference to Japanese Patent Laid-open No. 74668/1981 as prior art.
FIG. 3 shows a prior-art example of a scan pass type testing circuit with an asynchronous sequential circuit to be observed. In FIG. 3, reference numeral 35 denotes a block of a combination circuit, numerals 36 and 37 denote asynchronous circuit blocks each including a sequential circuit, numerals 8 to 16 denote scan registers provided between the circuit blocks, and numerals 26 to 34 denote data selectors for selecting any of the outputs of the corresponding circuit blocks and the outputs of the scan registers to output the selected output. The output signals of the respective circuit blocks are connected directly to the data input terminals D of the scan registers and the data input terminals D of the data selectors, respectively, and the output terminals Q of the corresponding scan registers are connected to the test data input terminals TD of the data selectors, respectively.
In FIG. 1, reference numeral 1 denotes a test mode selection terminal, which is connected to the mode selection terminals MS of the scan registers and the data selectors, respectively. Numeral 2 denotes a scan-in terminal, and numeral 38 denotes a scan-out terminal. The scan-in terminal 2 is connected to the scan-in terminal SI of the scan register 8, and the output terminal Q of the scan register 8 is connected to the scan-in terminal SI of the scan register 9. Thus, the output terminals Q of the respective scan registers are sequentially connected to the scan-in terminals SI of the next scan registers to resultantly form a shift register pass between the scan-in terminal 2 and the scan-out terminal 38. Numerals 3 to 5 denote ordinary data input terminals, numeral 6 denotes a scan clock input terminal, which is connected to the clock input terminals T of the scan registers.
FIG. 4 shows an example of the scan register shown in FIG. 3, symbol MS denotes a mode selection terminal, symbol D denotes a data input terminal, symbol SI denotes a scan-in terminal, and symbol T denotes a clock input terminal. Numeral 51 denotes an inverter gate, numerals 52 and 53 denote 2-input AND gates, numeral 54 denotes a 2-input OR gate, numeral 55 denotes an edge trigger D type flip-flop (hereinbelow referred to as "D-FF"), and symbol Q denotes a data output terminal.
FIG. 5 shows an example of the data selector shown in FIG. 3. Symbol MS denotes a mode selection terminal, symbol TD denotes a test data input terminal, symbol D denotes a data input terminal, numeral 60 denotes an inverter gate, numerals 61 and 62 denote 2-input AND gates, numeral 63 denotes a 2-input OR gate, and symbol Y denotes an output terminal.
The operation of the scan pass type testing circuit will be described.
The ordinary operation will be first described. In this case, a signal "H" is applied to the test mode selection terminal 1 (MS), and the scan clock terminal 6 (TS or T) is fixed to a voltage "L". As a result, the input and output terminals of the corresponding circuit blocks are connected directly through the respective data selectors.
This operation will be described with reference to FIG. 5. When a signal "H" is applied to the mode selection terminal MS of the data selector, the data from the data input terminal D is outputted through the AND gate 62 and the OR gate 63 to the output terminal Y. Since the output of the circuit block is connected directly to the data input terminal D of this data selector, the input and output terminals of the corresponding circuit block are connected directly.
The scan mode and the test mode are sequentially repeated as below at testing time to test the respective circuit blocks.